A recent video encoding technology involves dividing an image into blocks, predicting pixels contained in each of the blocks, and encoding the prediction differentials to achieve a high compression ratio. In this technology, a prediction mode for forming prediction pixels from the pixels within a picture subjected to encoding is referred to as “intra-prediction”, and a prediction mode for forming prediction pixels from a previously encoded reference image called “motion compensation” is referred to as “inter-prediction”.
In the video encoder, the inter-prediction expresses a region referred to as the predicted pixels with a motion vector composed of two-dimensional coordinate data including a horizontal component and a vertical component, and encodes prediction differential data of the motion vector and the pixels. In order to suppress an encoding amount of the motion vector, a prediction vector is generated from a motion vector of a block adjacent to the block subjected to encoding, and the differential vector between the motion vector and the prediction vector is encoded.
In Moving Picture Experts Group (MPEG)-4 AVC/H.264 (hereinafter also called “H.264”), which is a current provisioning video coding standard typically represented by High Efficiency Video Coding (HEVC), an address is assigned to each of the divided blocks in a raster order, and the processing order of the blocks is complied with the address order.
In the video encoding-decoding process, a large number of pixels is generally processed per second. In particular, motion compensation or orthogonal transformation may require high computational performance, and hence, it may be preferable that the video encoding or decoding process implement parallel processing. In the video encoding, there is a dependence relationship between the blocks for computing various prediction values from a block peripheral to the block subjected to encoding in a manner similar to the computation of the prediction vectors as described above. Hence, it may be difficult to perform parallel processing on the blocks.
A method for implementing parallel processing on the blocks without affecting the processing order or the dependence relationship between the blocks may, for example, include performing parallel processing by shifting a horizontal position of each of the processing blocks corresponding to the block lines.
In the following description, such parallel processing is called “parallel block line processing”. Next, a case where the parallel block line processing is performed corresponding to two block lines is described.
In order to perform parallel block line processing, a video processing device includes a unit 1 and a unit 2 each configured to independently process the corresponding block lines. For example, the unit 1 may be configured to process odd-numbered block lines, and the unit 2 may be configured to process even-numbered block lines.
FIG. 1 is a diagram illustrating an example of parallel block line processing. As illustrated in FIG. 1, a horizontal address of a block in a first block line processed by the unit 1 are shifted by two or more blocks from a horizontal address of a block in a second block line processed by the unit 2.
Thus, when a processing block X processed by the unit 2 is focused on, a block A on the left side of the processing block X is a processed block on which processing has been already performed. Similarly, a block B, a block C, and a block D processed by the unit 1 are processed blocks. The block B is on the upper left side of the processing block X, the block C is above the processing block X, and the block D is on the upper right side of the processing block X. The block X may be able to utilize encoded results of these processed blocks.
For example, processing on the even-numbered block lines may be able to start without awaiting the end of the processing on the odd-numbered block lines, and hence, the processing block X may be able to implement parallel processing associated with processing such as motion prediction or orthogonal transformation. In the above example, parallel processing of two block lines is described; however, the implementation of parallel processing is not limited to the parallel processing of the two block lines. In a case of parallel processing of N block lines, N units may be assigned to the N block lines in the video processing device.
Note that when parallel block line processing is executed as a program, a processing unit may be a thread, or a central processing unit (CPU).
According to H.264, entropy encoding may be carried out by processing a series of output bits in the order of processing blocks based on the standard specification. Hence, the video processing device temporarily stores results of the aforementioned parallel block line processing, and an entropy-encoder encodes the stored results in the order of processing blocks based on the standard specification.
By contrast, HEVC discloses a technology for interleafing a series of output bits between the block lines. FIG. 2 is a diagram illustrating an example of parallel block line processing performed by an entropy processing part in HEVC. As illustrated in FIG. 2, entropy encoding or decoding may be performed by parallel processing between the block lines.